High-speed electronic analogue-todigital converter system



March 5, 1957 Filed April 2, l

H. R. KAISER ET AL HIGH-SPEED ELECTRONIC ANALOGUE-TO-DIGITAL. CONVERTERSYSTEM I5 Sheets-Sheet l IN V EN TORS.

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March 5, 1957 H. R. KAISER ET AL 2,784,396

HIGH-SPEED ELECTRONIC ANALOGUE-TO-DIGITA-L CONVERTER SYSTEM Filed April2, 1953 s sheets-sheet 2 1 INVENTOR. 4f/@4a i. Mull,

United States Patent O i HIGH-SPEED ELECTRNIC ANALOGUE-TO- DIGITALCONVERTER SYSTEM Harold R. Kaiser, Woodland Hills, Claude A. Lane,Culver City, and Wilford S. Shockency, Torrance, Calif., assignors, bymesne assignments, to Hughes Aircraft Company, a corporation of DelawareApplication April 2, 1953, Serial No. 346,392 9 Claims. (Cl. 340-347)The present invention relates to analogue-to-digital converter systemsand more particularly to a high-speed electronic analogue-to-digitalconverter system for converting a plurality of analogue input signals tocorre` spending sets of digital output signals, the conversion beingperformed by forming one binary digit signal of the desired digital setat a time.

An analogue-to-digital converter is a device which accepts instantaneousvalues of variable quantities and eX- presses these values in discretenumerical form. in general, an electronic converter of this typeperiodically samples the instantaneous amplitude of an analogue inputsignal and expresses the amplitude of the sample in the ,form of a setof digital signals or a count.

Four general types of electronic analogue-to-digital tconverter systemshave been utilized in the prior art. In one type of converter system asample of voltage representing the analogue data to be converted is rstintro- .duced into a sampling pulse-width modulator which meas- `uresthe amplitude of the voltage sample with respect to .a bias voltage andgates out a pulse having a width proportional to the measured amplitude.This gate pulse controls a gate which is coupled between a clock-pulse.source and a pulse counter, the control being in such a .manner thatthe number of clock pulses passed to the .counter is substantiallyproportional to the width of the gate pulse. The clock pulse rate isdetermined by the maximum number of digits to be represented. For eX-ample, if the analogue data are to be represented by four binary digits,the clock pulse rate is set so that the maximum width of the gate pulseis equal to 16 times the period of the clock pulses. Such a convertermay be termed a counting converter.

A counting converter of the general type described above is shown in U.S. Patent No. 2,272,070, entitled Electric Signaling System by A. H.Reeves, issued February 3, 1942; and an improvement in this type ofconversion system is described and claimed in copending U. S. patentapplication Ser. No. 293,625, iiled June 14, 1952, en-

entitled Analogue-to-Digital Converter System by M. L. MacKnight.

ln general the counting converter requires 2N clock i pulse intervals toconvert an analogue input signal to an N-digit binary number; 2N clockpulse intervals being the cycling time of the counter- Where the counterincludes N flip-Hops, one for each binary digit desired. The 2N pulseinterval conversion period is required, whenever it is necessary to readthe digital setting of the counter' at a fixed time in a computingcycle, in order to allow for the conversion of a full-scale analogueinput signal. Thus, while it is theoretically possible to obtainconversions immediately after the counter has completed its operation,as a practical matter, a full 2N clock pulse interval is utilized foreach conversion.

A second type of electronic converter known in the prior art may bereferred to as a digit-at-a-time converter, since the analogue signal isconverted to a set of digital signals, one binary digit at a time. Onesystem jlilii Patented Mar. 5, 1957 of this general type is described inan article entitled `Telephony by pulse code modulation, by W. M.Goodall, in voi. XXVI of Bell System Technical intimal, January 1948, onpages 395-409.

ln the system described in the article by W. M. Goodal, the amplitude ofthe analogue sample is compared with a standard voltage representing themagnitude of the highest order digit of the digital set. if the standardvoltage is smaller than the sample, it is subtracted from the sample andthe remainder is then compared with a standard voltage representing thenext highest order digit. This process is continued until the lowestorder or units digit is compared with the remainder of the sample and isdetermined to be either larger or smaller. Each time the standardvoltage is found to be smaller than the sample, a binary 1 is recordedor transmitted; and each time the standard voltage is found to be largerthan the sample, a binary 0 is recorded and the standard voltage is notsubtracted from the sample.

in operation the digit-at-a-time converter requires only N clock pulsetime intervals for each conversion and, consequently, has the advantageof speed over the counting type of converter. The particular type ofdigitat-a-time converter described in the above-cited publication,however, is considerably more complicated than a counting type ofconverter, and is limited in accuracy due to the difficulty in obtainingseparate voltages accurately representing the magnitudes of the binarydigits; and due to the difficulty in accurately subtracting binaryvoltage increments from the analogue sample.

in a third type of input converter, hereinafter termed a continuousconverter, the amplitude of the analogue signal to be sampled iscontinuously compared with a variable reference voltage representing thedigital count in a counter. After each comparison, a signal is producedindicating the difference between the analogue potential and thereference voltage; the signal being then utilized to vary the count of acounter, and thereby the reference voltage, in single discrete stepsuntil the magnitude of the reference voltage and the analogue signal aresubstantially equal. Once this condition is reached the countercontinuously follows the variations of the analogue potential, andreadings are available after eX- tremely short time intervals. Acontinuous converter of this general type is described in U. S. PatentNo. 2,539,623, entitled Communication System, by R. A. Heising, issuedJanuary 30, 1951; and an improved type of continuous converter isdescribed and claimed in a copending U. S. patent application, Ser. No.272,784, entitled Analog-to-Digital Converter, by Cameron B. Forrest andSidney S. Green, tiled February 21, 1952.

Whenever it is possible to sample the analogue signal continuously, itis apparent that the continuous type of converter provides a veryhigh-speed conversion system. dn addition, that section of the converterwhich provides a reference voltage representing the digital count in thecounter may readily be used in an output converter, without theintroduction of a substantial amount of additional circuits. YThecontinuous type of converter, however, cannot operate at high speed in asystem where it is necessary to convert a plurality of analogue signalsto corresponding digital signal sets, and where there is no previousdigital record of the conversion of the analogue signals. Since in itsfastest operation the counter would be set at half scale and count up ordown, depending upon whether or not the analogue signal was greater orless than the reference voltage, it is clear that the continuousconverter requires at least ZN-l clock pulse intervals for eachconversion in a multiple analogue signal system.

Finally, a fourth type of yanalogue-to-digital converter measures theamplitude of the analogue sample and ,Of Operationhut renuirespci amagnitude be represented. y

producesV the corresponding digit pulses directly without intermediatecounting or subtracting. This type `of converter may be referred Ito asa direct converter, one lsuch converterrbeing shown in'rU. fS. PatentNo. 2,530,538, entitled ,Vernier P `,lse Code Communication 'Systemj byA. J. jRaclc, issued November 2,1, '1950. The converter described in thepatent torRaclr includes a cathode rayvtube providedr with Adetiectingelements for delflecting the beam, ,under control of an analogue signalsample to be coded, -to a particular aperture row. The aperture rows arearranged inracrcordance with the digital Vcode which is-representative'of the/,analogue signal sample. Thisgtype of converterprovides the highest speed v l structure such as cathode ray tubes andrequires a Vconsiderable amount of amplifying, Vd eecrting, andstabilizing circuits which are not otherwise required. n Y Y ,I Y l T hepresent invention provides an electronic analoguetti-'digitalConverters/Stem for nnrevrtine a plurality 0f ,analogue input signals tocorresponding sets of digital output signals, without the requirement ofa previous digitial record of the conversion of the analogue signals asis required in the continuous type of converter system. VThe converterof ,the presentV invention may be considered to be of thedigit-at-a-time described above, in thatyone binary digit is formulatedata time; the entire Vconversion requiring N clock pulse intervals.

Conversion, according to the present invention, however, isnotperformedin the manner described in the above-cited article by W. M.Goodall, 'since separate ,standard voltages are not generated foreach'of therdigits to be represented. Accordingto 4the present inventionthe digital number stored in a register, having as many ilip-ops thereinas the number of binary vdigits desired is continuously converted intoal corresponding reference signal. The reference signal is compared withthe analogue input signal in a comparator which produces a signalindicatinglthe ysense of difference4 between the reference signal andthe analogueinputsignal. Y Y In one manner of operation theV flip-Hopsot the register are initially sety so'th'at the highest place lhip-opregistersl l andVall `of the other nip-flops are in a O-representingstate. aV result,vtheA reference signal assumes i correspondingto thehighest order digit to The signal y produced by the l comparator thenYindicates whether or not "theanalogue input signal is larger than thereference signal. If the analogue input signal is larger than thereference signal, the highest placeV digit shoulcbbed and the setting ofthe 'highest place nip-flop ofthe register is not changed. `lf the senseofthe ycomparator signal indicatesthat the analogue Ainput signal is"smaller than the reference signal the highest place digitY is (ll/'andthe highest place flip-flop is resettoy 0. The lower place flip-flopsare then turned on,

l to lbe converted are applied tothe input circuity of the comparatorthrough separate electronic input switches which may be operated at`high speed without distorting the input signals,

The principal embodiment of the y'present invention comprises: a digitalnumber register having N iiip-ops,

ywhich are turned on one at a time during the converv sion operation; adigital-to-analogue decoding circuit for Y continuously producingareference signal lcorresponding to the digital'information in theregister; a comparator circuit, responsive to the reference Isignalandan applied analogue signal, for producing an output signal indicat- 1ing the sense of the difference Abetween thefreference signal and theanalogue signal; a plurality of electronic d a `time, in descendingorder, 'eachAipv-flop being set in accordance with the sense of thedifference resultingfrom the corresponding comparison.

amples.

input switches for selectively applying analogue input signals to theinput circuit of the comparator; and a control circuit for sequencingthe conversion operation according to a predetermined time-sharingbasis, and `for controlling the turning on and on" of the registerflip-Hops, in response to the comparator signal and to signals producedby the register nip flops.

Accordingly, it is lan object of the Vpresent invention to provide anVanalogue-to-digital converter system which includes simple circuits forconverting an analogue input signal into Va corresponding set of digitalsignals, vthe conversion being performed `by forming "oneYdigitrepresenting signal Vat a time.

Another object of the present invention is to provide an improveddigit-at-a-time converter system wherein no special circuits larerequired'for producing separate voltages representing binary digits andno special circuits are required for subtracting binary-weighted signalsfrom Vtlieanal'ogue inpi't signal.

An'additional object is to provide an analogue-to-digital convertersystem'for converting a plurality of analogue input signals tocorresponding sets/of digital output signals,'the conversin beingperformed without a'previous digital 'record `of th'econversion of theanalogue signals.

A further object is to Vprovide an analogue-to-digital convertersystem'wherein the 'conversion is performed by setting the stages 'of adigital number register, one ata time, under the control'of a comparatorcircuit whichprodu'ces anoutput signal corresponding to the differencebetween the Vanalogue representation ofk the register setting and theanalogue'signal to be converted.

The novel features which are believed to be characteristieof theinvention, both as `to its organization and method of operation,together with further objects and advantagesV thereof, 'willbe vbetterunderstood from the following description considered in connection withthe accompanying drawings in which several embodiments of the inventionare illustrated by way of ex- It is to Vbe expressly understood,however, that the drawings are for thepurpose 'of illustration and-description only, and arenot intended as a definition of the limits ofthe invention Fig. l is-a block diagram of the basic 'embodiment of the'present invention;

Fig. 2 is a block diagram of one' form of the Vdigital number registershown in Fig. l;

Fig. 3a isa schematic diagram of one form of the control circuit shownin' Fig. l;

Fig. 3b is a schematic diagram 'of another form of the control circuitshown in Fig. l;

Fig. 4 is a schematic'diagram of one form of the kdigital-to-analognedecoding circuit shown in Fig. l;

Fig. 5 isa schematic` diagram of one form of'the comparator shown inFig. l;

Fig. 6 is a composite diagram of the wave forms of signals appearing atvarious points in the embodiment of Fig. l during illustrativeanalogue-to-digital lconversion;

Fig. 7 is a schematic diagram of one form `of the input switch shown inFig. l.

Referring now to Fig. 1,'there is shown one embodiment'of ananalogue-to-digital converter system'according to the present invention,wherein analogue input signals are converted to corresponding digitaloutput signals, one digital signal being formed at a time. As shown inFig. Ltne converter comprises: aY digital number register 290, which isYto be set toV the digital number desired; a decoding circuit 300,connected to register 200. for continuously producing a reference signalcorresponding to the digital setting of register 200; a comparatorcircuit ,ei-titi, responsive to the reference signal and to ananalogue-input signal applied through one of separate inputswitches 560,for producing a signal C0 indicating Vthe vsense ofthedierencebetween'the reference signal. and the `analogue' input signal; and acon- 0 states, respectively. The same of 'the other signals to theiroriginating bistable circuits.

trol circuit 600, responsive to signal Co, for producing signals toactuate register 200 so that it is set one digit at a time during theconversion. Control circuit 600 also produces timing signals forsequencing the switching in of analogue input signals.

rMany of the circuits which are utilized in the embodiment shown in Fig.l are mechanized according to logical equations, these equations beingdetermined through a logical consideration of the manner in which theconversion is to be performed. Consequently, the invention is morereadily undersood by first considering the manner in which theconversion is to be performed, then deriving the defining logicalequations, and finally considering the details of specific circuits.

In the analysis which follows it will be assumed that register 200produces N pairs of complementary digital signals representing the Ndigits of the number desired, and designated as R1, R1; R2, R2; R3, R3;and Rn, R11, respectively. One form of register suitable for providingthe digital signals is illustrated in Fig. 2 wherein it is noted thatregister 300 includes n flip-flops R1, R2; R3 and Rn, producingcomplementary output signals R1, R1; R2, R2; R3, R3; and Rn, Rn;respectively, and having 1 and 0 input circuits designated as 1R1, 0R1;1R2, 0R2; IRS, 0R3; and lRn, 0R11, respectively. The input circuits ofeach flip-flop are arranged so that separate application of signals tothe l and 0 input circuits set the flip-flop to stable statesrepresenting binary l. and 0, respectively; and simultaneous applicationof signals to both input circuits, triggers, or reverses the stablestate of the Hip-flop. The arbitrary convention will be adoptedthroughout the following description that the high and low levels of adigital signal will be designated as the 1 and 0 levels, respectively.An arbitrary convention will also be adopted relating the l and 0 levelsof a signal to the 1 and 0 states of the flip-flop originating thesignal. For the signal Rn, for example, the convention is adopted thatsignal Rn is at its 1 and 0 levels, respectively, when the originatingbistable Rn is in its corresponding 1 and 0 states. Complementary signalRn, on the other hand, is at its 0 and 1 levels, respectively, whenflip-flop R11 is in its corresponding 1 and conventions relate each Itwill be noted that the leads shown in Fig. 2 are designated by thesignals appearing thereon, as illustrated by lead Rn which receivesoutput signal Rn from flip-flop Riz. ,-Tliis convention is followedthroughout this specification so that the algebraic mechanizationequations which are given below may be interpreted directly as thecircuit connections which are shown in the figures. In addition, it willbe noted that the leads coming from control circuit 600 are numberedaccording to the flip-flop input circuit to which they are connected.Thus, lead 1K3 is connected to input circuit 1R3 of flip-flop R3.

In preforming a digit-at-a-time conversion, the binary digits of thedesired digital set are formed in descending order of place, startingwith the most significant binary digit. There are two basic methods ofoperation for forming the binary digits in this manner. In a firstmethod of operation the flip-flops of register 200 are initially set to0 and are then set to 1, in descending order of place, one flip-flopbeing set to 1 at the beginning of each clock-pulse period. At the endof each clock-pulse period, then, the flip-flop which has just been setto 1 is reset to 0 if signal Co is l, otherwise it remains in its 1state.

According to the second basic method of operation, the flip-flops ofregister 200 are initially set to l and then are set to 0, in descendingorder of place. At the end of each clock pulse period, then, theflip-flop which has just been set to 0 at the beginning of thecorresponding clock-pulse period is reset to 1 if signal Co is 0,otherwise it remains set to 0.

In either method of operation it is possible to eliminate oneclock-pulse period of operation by initially setting flip-flop Rn to thestate it is to assume during the first period of the conversionoperation. Thus, in conversion according to the first method flip-Hop Rnis initially set to l and flip-flops R1 through Rn-l are set to 0; andin conversion according to the second method flip-flop Rn is initiallyset to 0 and flip-flops R1 through R11-1 are set to 1.

When the converter is to be utilized in a computer system it isfrequently necessary to synchronize its operation with the computeroperation by utilizing the computer synchronizing pulses, hereinafterreferred to as pulses Cp, to control the conversion operation. Thus, inone form, the converter of the present invention is controlled byvoltage-level timing signals Ti and the computer synchronizing signalsCp. Although there are many other methods of timing, it will be assumedin the discussion which follows that voltage-level timing signals Ti andpulses Cp are utilized to sequence the conversion operation.

Since there are N clock-pulse periods of operation, N+1 timing signalsare required for sequencing the operation; N timing signals beingutilized to control the application of pulses Cp at the beginning of theclockpulse periods, respectively, and the (N+1)st timing signal beingutilized to control the application of a pulse Cp at the end of theconversion operation. N of the timing signals are designated as T1through Tn and have levels representing binary l prior to the firstthrough the Nth clock-pulse periods, respectively; and the (N+l)sttiming signal is represented as Tn+1 and has `a level representingbinary 1 during the last clock-pulse period. In addition, it isconvenient to define the timing signal Tij as representing any of thetiming signals Tf1 through Tin.

Where the Hip-flops of register 200 are utilized for other operationswhen it is not the analogue-to-digital conversion period it is necessaryto prevent the application of signals to the flip-flops according to theconversion logic. One method of achieving this is through theutilization of a `signal Ad, having a level representing l only duringthe analogue-to-digital conversion period, and a level representing 0 atall other times. The signal Ad, then, is utilized in the logicalequations appearing below to limit the application ofyanalogue-to-digital conversion signals to the proper period.

According to the first method of operation discussed above, then,dip-flop Rn is yset to l at the 'beginniugof the analogue-to--digitalconversion period (Ad=l) if signal Til is l and pulse Cp is applied tothe converter. This relationship may be expressed algebraically as:

c2.) 1 iRnAdnfaCp milenaria-cp In set-(1) above it is noted that signalTil appears in Vfunction lRri and vin functions -tlRl through @Rm-1, j

representing `any of the integers: 1 through n-l. Thus, .flip-flop Rn isYinitially -set to 1 and Hip-flops R1 through R11-1to0. Similarly, vinset (2), signal Til functions to set ip-op Rn vto 0 and flip-flops R1through Riz-1 to 1.

According to the equations of set (l), then, ip-op Rj is set -tofl aftertiming signal TX is 1 and a pulse Cp Yis applied; and is then set to 0after signal TPJrl is 1, if signal Co is 1 and pulse Cp is applied.Thus, if n is equal to A8, ylipV-op R2 is set to 1 after timing signalTi6 ris 1 and is then set to 0 .after timing tignal Ti'l is l, if signalCo is .1 and `pulse Cp is applied. in a similar manner, according to theequations of set (2), ip-ops Rj are set to 0 after timing signal TiX isl and arethen set -to `1 after signal Tixrl is 1, if signal Co is 1.

The :timing signals utilized in .the above equations may he derived froma .counter which counts the number .of

'applied pulses Cp. While this arrangement may be satisfactor-y inafcomputer 4system which already includes a fcounter, in-other cases itmay require additional flip-hops which, it will be shown, are notnecessary since the timing Vsignals may be derived from the flip-flopsof register 200. While ythe basic concept of the invention is notlimited to a system wherein the timing signals are derived from theregister, this `arrangement is a novel feature of one of the species.

Since, according to the equations of set (1), each indicating that TX isl after ip-llop yRj-l-l is set to 1, but beforelany of the ip-ops R1through R1' have been set to l. In a similar manner, timing `signal TMl'becomes 1 after flip-flop Ry' is set to 1, but before flip-hops R1through Rj-l are set to 1. Thus,'TX+l is defined as follows:

Tr+1=Ri.'1-1 R1 From this analysis it should ybe apparent that timingsignals Tx and TXfl, for'the system dened by equations of set (2)V maybe defined inthe following manner:

It will be noted that the function lRj includes thelsignal nl,indicating that whennip-nop Rits 1 (15:0) no Signat is applied to theltinput circuit thereof* It may be seen, then, that signal TU issuperluous since if flip-op Rjzis .already in a 1representing state itis permissible to allow the application of a signal to its 1 inputcircuit since this causes .no change. Thus, signal l may be replacedwith 1 in functions TR1', above. Ina similar manner, the signal 'fRl Aissuperuous in the function 0K1' since it is permissible to apply a signalto the 0 input circuit lof vipflop Rj if itis already set to O asindicated by Rj 'being equal to 0. Substituting 1 for in the functions1Rj and 1 for RJ in the functions 0Rj, the equations of .set (1) and (2)become:

The manner in which specific circuits are mechanized according to thedefining algebraic functions given above is illustrated in Fig. 3a whichshows one form of the control circuit 6th) of Fig. l. Referring now toFig. 3a, it is noted that signals Ad, Til and Cp are produced by asignal generator 611i). rEhe waveforms of signals Cp, Ad and Ti1 areillustrated in Fig. 6, where the other waveforms shown are those whichoccur during operation which is described in detail below. Signalgenerator dli is not shown in detail, since such circuits are well knownin the art.

Control circuit 696 also includes a control matrix 620 which providesthe input signals controlling the register flip-flops. It will be notedthat for purposes of simplicity, input signals for only four flip-ops,R1, R2, R3, and R4, are shown in Fig. 3a, although any number of ip-opinput signals may be provided in the same manner. The defining algebraicequations for matrix 620 are:

Each of the and functions in these equations is provided by an andcircuit, such as and circuit `621, providing the signal Ad.T1.Cp whichis applied to flip-flop input circuit 1R14. And circuit 621 responds tosignals Ad, Til and Cp applied to separate input terminals and producesa signal Ad.Ti1.Cp=l, when signals Ad and Til are high-level signalsrepresenting binary l and a pulse Cp is applied. Each of the orfunctions is provided by an or circuit, such as or circuit 622 whichprovides a. signal for input circuit ORS. Or circuit 622 produces alrepresenting signal when either or both of signals Rill-LC@ and Ti,applied to separate input terminals, are 1representing signals. Thesignal R2.R1.C0+Ti1 is combined with signals Aa and Cp in and circuit623 which produces the signal Ad.(R2.R1.Co-{T1).Cp. The manner in whichthe other and and or circuits are mechanized, according to thecorresponding equations, should be apparent from the examples alreadyconsidered.

And and or circuits for providing the abovedescribed operation are wellknown in the computer art; suitable circuits, for example, being shownon pages 37 to 45 of High-Speed Computing Devices by EngineeringResearch Associates, published in 1950 by McGraw-Hill Company, Inc., NewYork and London, and in an article entitled Diode coincidence and mixingcircuits in digital computers by Tung Chang Chen in vol. 38 of theProceedings of the Institute of Radio Engineers, May 1950, on pages 511through 514.

Where register 266 includes a large number of flip-hops and the timingsignals are derived from the hip-Hops, in the abovedescribed manner, thelower place ip-ops may a particular input conversion be rather heavilyloaded. Thus, with eight flip-flops (11:8), signal .Rl appears in seventiming signalsplacing a heavy load on fiip-op =1. This situation may beavoided by storing part of the timing function in an additional iiip-opwhich functions as a buffer between the lower-place register ip-iiopsand the load. Where eight iiip-ops are utilized, for example, thefunction Ad.R4.R3.R2.R1, may be stored in a buffer ip-op, hereinafterreferred to as flip-flop Adl, in the manner indicated by the followingequations:

According to these equations hip-lop Adl is set to 1 after Ad is 1 andpulse Cp is applied, and is set to 0 during the conversion (A6121),after signal R5 is l, or just prior to Rl is set to l. Thus, the signalAdl produced by ip-tlop Adi may be dened as follows:

AaliAdJ-erar-el since signalAd1 is l during the period that Ad is 1,except that it becomes 0 after R5 is 1 and remains O during theA periodthat any of signals R4, R3, R2 or R1 are 1.

Gne form of control circuit for a system including eight flip-ops and abuffer iiip-iiop Adi., is illustrated in Fig. 3b and is mechanizedaccording to the following equations: iRszAdrftCp ens=xalueacacpimzAaaRsiGcp eRlz/idluacwrfocp The manner in which ing to theseequations amples already considered and therefore will not be consideredfurther.

During the time that the lijp-flops of register 200 are being turned onor ott under the control of signals produced by control circuit 600,decoding circuit 300 continuously produces an output signal indicatingthe setting of register 200. Decoding circuit 309 may be any of thewell-known types of circuits for providing an analogue signalrepresentation of a digital number. A suitable decoding circuit forexample, is described and claimed in copending U. S. patent application,Serial No. 239,077, entitled Digital-to-Analog Converter by SiegfriedHansen, tiled July 28, 1951, now Patent No. 2,718,634, issued September20, 1955. It is preferred, however to use a. decoding circuit of thetype shown in Fig. 4 of this specication. The description in thisspecification concerning the decoding circuit of Fig. 4 is brief, sincethe circuit is described in greater detail in copending U. S. patentap-4 plication, Serial No. 346,393, filed April 2, 1953, entitled matrix620 is mechanized accord- High-Speed Electronic Digital-to-AnalogueConverter- System, by C. A. Lane, W. S. Shockency and H. R. Kaiser,wherein another species of this type of decoding circuit is alsodescribed. This is now Patent No. 2,736,889, dated February 28, 1956.

As shown in Fig. 4, decoding circuit 300 comprisesl aJ plurality ofcurrent switches 310; n switches being shown.

should be apparent from the ex corresponding to the n ilip-ops inregister 200 respectively, Each of the current switches S10-j (j beingany of the integers 1 through n) has an input terminal B11-j, an outputterminal 312-j, and a control terminal 313-1'. A source of positivepotential, not shown, is applied to input terminal 311-1' and outputterminal S12-j is coupled to ground through a first current-Weightingresistor 31A-ij. signal r, produced by nip-ddp nf, is applied to controlterminal 313-1' and is effective to control the switch in a manner to bedescribed. Output terminal S12-j is also coupled through a secondcurrent-weighting resistor 315-1' to common output line 350, which isconnected to the input circuit of comparator 400, described in detailbelow.

Each yof current switches 310-1 is open when the signal Rj applied tocontrol terminal S13-j is at a high level, indicating that thecorresponding flip-flop registers Y a 0, and is closed when signal Ri isat a low level, in-

dicating that the corresponding flip-op registers a l..

When l, and current switch S10-j is open, no current passes througheither of current-weighting resistor 314-j or 315-1 whereas when signalRi=0, current switch 310-1' is closed and current flows throughresistors 314-1', and 315-1'.

Resistors S14-j and S15-j are selected so that when the input conversionis completed the current through resistor 315-1 has a valuecorresponding to the binary weight of the digit stored in Hip-flop Ri.

the voltage on output line 350 is volts at the end of the inputconversionperiod and consequently the values of resistors 314-1 and315-1' are readily computed on the basis of a given source voltage andcurrent switch im- Complete details as to circuit values andpotenpedance. tials are given in the above-mentioned copendingapplication for High-Speed Electronic Digital-to-Analogue ConverterSystem.

In one form, each of current switches may be of the type illustrated forcurrent switch S-n. As shown in Figure 4, current switch 3110-11comprises a triode 316 having its control grid connected through .aresistor 317 to control terminal 313-11 and connected through a resistor318 to a source of negative biasing potential, not shown. The biasingpotential is selected so that with `signal R in its high-level staterepresenting binary 1 triode 316 conducts, and with signal R in itslow-level state triode 316 is cut off.

The anode of triode 316 is coupled through a loa-d resistor 319 to asource of positive potential, not shown, and to the cathode of a diode320. The anode of diode 320 is coupled through a resistor 321 to inputterminal 311-n. The cathode of triode 316 is connected to a source ofnegative potential, not shown, which is selected so that conduction oftriode 316 lowers the potential appearing at the anode of diode 320 to anegative value. The anode of diode 320 is also connected to the anode ofaV second diode 322 which has its cathode connected to output terminalS12-n. Y

In operation, whenever signal Rn is vhigh and triode 316 is conductingthe potential appearing at the anode of diodes 320 and 322 issuiiiciently negative to bias diode 322 so that no current may passthere through. Thus, the currentV switch is open when signal Rrepresents binary 1, and Hip-flop Rn registers 0.

When signal Ri is at a low level indicating that ilipflop Rn registers a1, triode 316 is cut off, with the result that the anode potentialthereof rises to a level which is high enough to bias off diode 320. Asa result, diode 322 is no longer biased oit and conducts, allowing abinaryweighted current to flow through register 315-11, whichconstitutes closure of the switch.

Since a binary-weighted current passes Vthrough each As will be morefully understood when comparator 400 is considered in detail,

' l2 Y current switch 310-j when it is closed under the control of theassociated iiip-ilop signal Rf=0, it is apparent that the total currentpassing through all of the current-weighting -resistors 3715 correspondsto the binary setting of register 200. The currents passing throughresistors 315 are added in output lead 350 which is connected to theAinput circuit of comparator 400, one embodiment of which is shown inFig. 5. It should be apparent now that the current signal which ispresent in lead 350 is,

the reference signal above referred to.

Consider now the manner in which comparator 400, shown i-n Fig. 5,produces signals C0 and C0 as a function of the sense of the differencebetween the reference signal :and an applied analogue input signal.Referring J now to Fig. 5, it is noted that the reference signal and theanalogue signal to be converted are applied to first and second inputterminals 401 and 402 of comparator circuit 400. Input terminal 401 isconnected via lead 405 to t-he input circuit of a drift-stabilized D. C.arnplier circuit 410, and input terminal 402 is connected to the inputcircuit of D. C. inverting amplifier' 420, ampliiier 420 being alsodrift stabilized and producing an amplified output signal whichcorresponds to the applied analogue input signal but having an oppositepolarity or sign. The output circuit of amplifier 420 is coupled throughan adding resistor 430 `to lead 405, the junction 435 created therebybeing hereinafter referred to as an add point.

Amplier 410 produces a signal which corresponds to the `differencebetween the reference signal and the analogue signal, the differencesignal being then applied to the input circuit of a D. C. triggercircuit 440. Trigger circuit 440 has iirst and second output circuitsproducing signals C0 and C0, respectively. Signals Co and Co have levelsrepresenting binary l and 0, when the sense of the diiference betweenthe reference signal Vand the applied analogue input signal is positive,and 'have levels representing binary 0 and l when the sense of thedifference is negative.

D. C. amplifier circuits suitable for use in comparator 400 are wellknown in the art; illustrative types of circuits, for example, beingshown and described in an article entitled Driftless D. C. amplifier byFrank R. Bradley et al. in vol. 25 of Electronics, April 1952, on pages144 through 148. Similarly, D. C. trigger circuits of the type requiredfor trigger circuit 440 are well known, a suitable circuit, for example,being known as a Schmitt trigger circuit. Such a circuit is described inan article entitled A thermionic trigger by G. H. Schmitt in volume X'Vof I ournal of Scientic Instruments, 193 8, on pages 24 through 26.

Adding resistor 430 in comparator circuit 400 is selected so that withthe analogue input signal at its fullscale value and register 200 set sothat all ilip-lops are in a l-representing condition, the currenttherethrough is suicient to cause the potential of add point 435 tostabilize at substantially zero volts. Thus, if a full-scale analoguesignal causes the output voltage of amplifier 420 to fall to a potentialof 50 volts, and if the sum of all currents through resistors 315 indecoding circuit 300 is 2 milliamperes, then adding resistor 430 is25,000 ohms.

With a linear variation of the output voltage of amplitier 42() inresponse to changes in the analogue input signal, it is apparent thatthe add point potential will stabilize at substantially zero voltswhenever the setting of register 200 represents the digital equivalentof the analogue input signal. The potential at the add point, however,may differ from zero by an amount which is equivalent to the analoguerepresentation of the least significant binary digit, without reducingthe accuracy of the system.

It should be understood, then, that with a decoding circuit of the typeshown in Fig. 4, the potential appearing atadd point 435 is positive,when the setting of register 200 represents an analogue signal greaterthan the analogue input signal, and tnat the add point potential isnegative, when the setting of register 206 represents an analogue signalwhich is less than the analogue input signal. As is more fully explainedin the abovementioned copending application entitled, High-SpeedElectronic Digital-to-Analogue Converter System, however, the decodingcircuit 390 may produce negative currents corresponding to the settingof register 200 and, when this type of decoding circuit is utilized, theVoltage at add point 435 is inverted with respect to that justdescribed. In the discussion that follows, however, it will be assumedthat positive and negative potentials appearing at add point 435indicate that the reference signal is greater and less than the analogueinput signal, respectively.

The accuracy of the conversion system is a function of the number ofbinary digits which may be correctly produced. if N binary digits arecorrect then it may be said that the system is capable of reproducingthe analogue input signal as a binary number to within an error range of1/zNil times the full-scale analogue signal. This may also be referredto as an N-digit accuracy, where N-l digits of the binary result areassumed to be correct, and the least significant digit is correct towithin one-half a digit.

The most critical test of the converter system is as to whether thecomparator circuit can accurately sense a difference signalcorresponding to one-half of the least significant binary digit. Thissensitivity cannot be achieved if the comparator is biased at zero voltssince the analogue input signal may be just slightly less than a binarynumber having a 1 in the least significant place and, when iiip-liop R1is turned on (according to method (1)) trigger 440 is set to 1 andflip-flop R1 is set to 0. This operation thus produces an error which isgreater than one-half of the least significant digit.

It is apparent, then, that to maintain the N-digit accuracy trigger 440must be biased so that it is not set to 1 unless the difference signalapplied thereto is greater than one-half of the least significant digit.Where a positive-signal decoding circuit is utilized trigger circuit 440is biased negatively by an amount corresponding to one-half of the leastsignificant digit so that it triggers when the applied signal ispositive by the corresponding amount; and, similarly, where anegative-signal decoding circuit is utilized trigger circuit 44() isbiased positively by an amount corresponding to one-half of the leastsignificant digit.

Considering now an illustrative operation of the input conversioncircuits of Fig. 1, reference being also made to Fig. 6 wherein certainwaveforms occurring during this operation are shown. For simplicity itis assumed that the analogue input signal is to be converted to a fourdigit binary number and, consequently, register 200 includes only fourHip-flops R1, R2, R3 and R4, the output signals of these Hip-flops beingrepresented, in- Fig. 6, by waveforms R1, .2, R3 and R4, respectively.

In the particular operation which is to be illustrated the analogueinput signal is assumed to be a S-unit signal, where each unit is theanalogue equivalent of the least significant binary digit in the digitalnumber desired.

As shown in Fig. 6, iiip-tiop R4 is set to l and ip-liop R1 through R3to 0 at the occurrence of the first clock pulse signal Cp after signalTil assumes a l-representing level. It will be noted that prior to thestart of the input-conversion operation signals R1, R2, R3, and R4 areshown as having levels intermediate to 1 and 0 in order to indicate thatmay be in either state depending upon howthey are left after the end ofthe preceding operation. It should be understood, however, that there isactually no intermediate level.

As flip-flop R1 is set to 1 the reference signal produced by decodingcircuit 300 assumes an 8-unit level corresponding to the analoguerepresentation of the most significant binary digit. Since the analogueinput signal is only a 5 -unit signal, the dierence signal at add pointS35 is approximately a positive 3-unit signal (approximate since thereference signal does not accurately represent the register settinguntil the add point potential is 0 volts). The positive potential at addpoint 43S causes trigger circuit 440 to register binary 1 andconsequently the comparator output signal Co assumes a level of 1.

At the end of the first clock pulse period of operation, flip-liep R4 isset to 0 in response to the application of the second clock pulse signalto the gate which provides a signal for input circuit 0R4, since signalC0 is 1 while iiip-liop R3 is set to l in response to the application ofthe same second clock pulse signal to the gate which provides an inputsignal for input circuit 1R3. Because the R4 ip-iiop requires a finitetime to change state, the R4 signal is, of course, still being fed tothe 1R3 gate at the time the second clock pulse is applied to the 1R15gate. Signal Co then becomes O since the add point potential becomesnegative, representing the difference between an analogue input signalof 5 units and the 4-unit weight of flip-flop R3.

Flipdiop R3 is not turned to 0 at the end of the correspondingclock-pulse period since at this time signal Co is 0 and a pulse is notapplied to input circuit 0R3. Flip-flop R3, then, remains set at 1,indicating that third digit of the binary conversion is 1.

Flip-iop R2 is turned on at the beginning of the third clock-pulseperiod of the input conversion and is turned off at the end thereof,since the add point signal goes positive and signal Co becomes l.Finally, during the fourth period of the input conversion, the add pointpotential is substantially 0 volts and trigger 440 remains set in aO-representing stable state. Thus, dip-iop R1 is set to l, but is notset to 0 at the end of the fourth clock-pulse period. At the end of theinput conversion, then, it is apparent that register 20) is set so thatit represents the binary number 0161, which corresponds to the S-unitanalogue input signal. It will also be noted that signal C0, producedduring the input conversion, is the complement of the setting ofregister 200 so that signal CNU may be utilized to provide a serialsignal corresponding to the conversion of an applied analogue inputsignal.

Where a plurality of analogue input signals are to be converted tocorresponding sets of digital signals, each analogue signal is coupledto the input circuit of comparator 490 through a separate input switch500; input switches 590 being opened and closed under the control ofsignals produced by control circuit 660. One type ot' circuit suitablefor use in input switches 500 is illustrated in Fig. 7.

Referring now to Fig. 7, it is noted that input switch Sti() includesfirst and second input terminals 501 and 502; the analogue signal to beconverted and a control signal produced by control circuit ad@ beingapplied to input terminals Stil and 592, respectively. input terminal Slis connected to cathode of a first diode. 5(13 having its anode coupledthrough a load resistor Still to a source of positive potential, notshown, the potential applied to 'esistor :30d being greater than thefull-scale level of the analogue input signal. The anode of diode 503 isalso connected to the anode of the second diode 505 which has itscathode connected to an output terminal 5&6; output terminal 566 beingconnected to the input circuit of comparator 404). The junction 5t7 ofdiode 563 and 505 is connected to the anode of a triode 503 having itsgrid coupled through coupling capacitor 509 to input terminal 562, thegrid of triode 56S being also coupled through a load resistor 510 to itscathode. The cathode of triode 503 is connected to a source of negativepotential, not shown.

ln operation, triode 593 is normally conducting so that junction 507 isheld at a negative potential which biases diode 503- and 50S so thatthey are rionconducting and. in effect, switch 597 is open When anegative signal is applied to input terminal 502, triode 508 is cut ofi,diode 593 becomes forward biased, and junction 567 rises to a valuewhich is substantially equal to the value of the analogue signal appliedto input terminal Sill, since the potential drop across diode 5493 isnegligible. The signal appearing at junction 597 then is transmittedthrough diode 5%5', with substantially no distortion, to the inputcircuit of comparator 40d.

When a plurality of input switches of the type described above areutilized, a short period is allowed prior to each input conversion toinsure that the output signal of the corresponding switch rises to thelevel or" the 'associated analogue input signal. The rise of the switchoutput signal may, for example, be delayed due to shunt capacity acrossthe parallel-connected switches. A set of typical Vwaveformsillustrating the operation of a pair of input switches, during two inputconversions is shown in Fig. 6, the pair of input switches comprising arirst input switch and a second input switch, each switch beingidentical to switch 500.

waveforms Ti and Afl', shown in Fig. 6, correspond to signals T1' and Addiscussed above except that they are periodic. waveforms 602-1 and 662-2represent the signals applied to input terminals 502 of the irst andsecond switches, respectively. It will be noted that wave- Y form 602-1;becomes negative, closing the rst switch,

a short interval prior to the rst high-level portion or' signal Ad', andwaveform 602-2 becomes negative closing the second switch a shortinterval prior to the second high-level portion or signal Ad', each ofsignals 692-1 and 692-2 then remaining negative throughout thecorresponding input conversion period.

The input converter circuits of the data conversion system operate inthe same manner where a plurality ot' analogue signals are to beconverted as where only one signal is converted. Thus, it is not deemednecessary to reconsider the input conversion operation which has beendiscussed in detail above.

From the foregoing description it is apparent that the present inventionprovides an improved digit-at-a-time converter system which includessimple circuits for converting an analogue input signal into acorresponding set or digital signals, no special circuits being requiredfor subtracting binary-weighted signals from the analogue input signal.lt should also be evident that the invention provides a high-speedelectronic system for performing conversions without a previous digitalrecord of prior conversions as is required for a continuous type oconverter; and that the conversion may be completed in N clock pulseintervals, where N is the number of digits in the binary number desired.As a result, the system of the present invention maires it possible toconvert a considerable number of analogue signals to correspondingdigital signals with simple circuits utilized on a timesharing basis.

For Simplicity the invention has been described with Y particularitywith respect Yto embodiment wherein conversions are made to 4-digitbinary numbers. it should be understood, however, that Vthe principlesdescribed herein are applicableV to systems adapted to convert to binarynumbers of other digit lengths. ln a similar manner, it should beapparent lthat the number of input conversions which the system has beendescribed as handling has been selected for illustration purposes only.

Specific formsof circuits suitable for decoding circuit 30?, comparatorcircuit 40%, and input switches 5%, have been described in detail; andother forms of suitable circuits have incorporated by reference torelevant publications. l t shouldV be understood, however, that thebasic concept of the invention is not limited to the specie circuitsconsidered. l Y

In a similar manner it is apparent that the circuits of control circuit60d which are defined by the algebraic equations considered above may bereplaced by others which are dened by a `different set of equations. Ithas been pointed out, for example, that the equations defining theconnections for matrix 620 shown in Fig. 3a and in Fig. 3b, may bereplaced with equations which define an imput conversion wherein theilip-ilops of register 200 are turned on one at a time under the controlof signals produced by a timing counter.

Thus, it will be apparent to one skilled in the art that there are manyanalogue-to-digital conversion systems which may be designed accordingto the present invention Without departing from the spirit thereof.

What is claimed as new is:

l. A high-speed electronic analogue-to-digital converter for convertingan analogue input signal to a corresponding set of digital outputsignals, said system comprising: a digital number register including aplurality of flip-flops, one for each digit of the digital signal set,said ip-ops being operable to produce signals corresponding to saiddigits, respectively; a decoding circuit coupled to said register forcontinuously producing an analogue reference signal corresponding to thedigital information in said register; a comparator circuit coupled tosaid decoding circuit and being responsive to said reference signal andto the analogue input signal for producing complementary signals Co andC0, respectively indicating the positive and negative sense of thedifference between the analogue signal and the reference signal; acontrol circuit coupled to said comparator circuit and to said registerfor setting said flip-hops, one at a time in descending order of place,to stable states representing the digital equivalent of the analogueinput signal, said control circuit including first means for initiallysetting said flip-dips to one stable state, second means forsequentially setting said flip-flops to the other stable state, andthird means coupled to said comparison unit and operable in response toone of said complementary signals for resetting said flip-hops to saidone state after said lip-ops are set to said other state, respectively.

2. The system defined in claim l wherein said one stable is theO-representing stable state of said flip-hops, said other stable stateis the l-representing state of said p-llops, and said one complementarysignal is signal C0.

3. An electronic converter for forming a set of N digital signalscorersponding to an analogue input signal, one digital signal of saidset being formed at a time in descending order of place, said convertercomprising: a register including N llip-llops operable to produce Nsignals corresponding to said digital signals, respectively; rst meanscoupled to said register for continuously producing a reference signalhaving a level corresponding to the setting of said register; secondmeans coupled to said lirst means and responsive to said referencesignal and to the analogue input signal for producing comparator signalsC0 and Co when said reference signal is greater and less than saidanalogue signal, respectively; and third means coupled to said registerand said second means for applying the analogue input signal to said Ysecond means, said third means including apparatus for nitially settingsaid Hip-ops to one stable state, and for then sequentially setting saidtlip-ops in descending order to place to the other stable state, saidapparatus being actuable in response to one of said comparator signalsfor resetting said hip-flops to Said one stable state after saidilip-ops are set to said other state, respectively.

4. The converter dened in claim 3 wherein each of said Flip-flopsincludes a l and a 0 input circuit and produces complementary outputsignals; and wherein said third means includes a plurality of and and orcircuits mechanized according to a predetermined set of logicalequations, one for each of said input circuits, said equations includingvarables representing said complementary output signals, respectively,and defining the circuit connections to said input circuits, theequations defining the l-nput circuitl connections determining thesetting of the associated ilip-iiop to l and the equations defining theO-input circuit connections determining the setting of the associatedliip-ilop to 0.

5. The converter defined in claim 3 wherein said second means includes adirect-current trigger circuit for producing signals C and Cnt-i havinglevels representing binary l and 0 when said trigger circuit is 'n al-representing stable state and having levels representing binary 0 andl when said trigger circuit is in a (It-representing stable state; saidtrigger circuit being set to l-representing and O-representing states,respectively, when the sense of the difference between said referencesignal and said analogue signal is positive and negative; and said thirdmeans being actuated in response to said l-representing level of signalCo to reset said bistable devices to said one stable state.

6. A high-speed electronic conversion system for converting an analogueinput signal to a corresponding set of digital signals, said systemcomprising: a plurality of bistable devices, one for each digital signalof said set, said devices having two stable states and being operable toproduce signals corresponding to said digital signals, respectively; adecoding circuit coupled to said devices for continuously producing areference signal having a level corresponding to the digital setting ofsaid devices; a comparator coupled to said decoding circuit andresponsive to said reference signal and to the analogue input signal forproducing a two-level signal indicating the sense of the differencebetween the analogue signal and the reference signal, said two-levelsignal having first and second levels when said reference signal isgreater and less than said analogue signal, respectively; and a controlcircuit coupled to said bistable devices and to said comparator forsetting said bistable devices, one at a time in descending order ofplace, to a set of stable states representing the digital equivalent ofthe analogue input signal, said control circuit including first meansfor initially setting said bistable devices to one of said states,second means for then setting said bistable devices in sequentiallydescending order to the other of said states, and third means, actuatedin response to said first level of said two-level signal, for resettingeach individual bistable device of said plurality of bistable devices tosaid one state, respectively, after the corresponding bistable devicehas been set to said other state.

7. The-system defined in claim 6 wherein said one and other stablestates are the 0 and 1 representing stable states, respectively, of saidflip-flops, and said first means includes a plurality of and and orcircuits mechanized according to a predetermined set of logicalequations defining an analogue-to-digital conversion wherein said ip-opsare initially set to 0-representing stable states, `and are then set tol-representing stable states in descending sequence, the ip-liops beingreset to O-Iepresenting stable states in response to signal Co.

8. A high-speed electronic digit-at-atime converter for translating ananalogue input signal to a corresponding set of N digital outputsignals, said converter comprising: a digital number register includingflip-Hops R1 R1', and Rn, J representing any of the integers l throughn, each of said flip-flops RJ' being operable for producing signals RJ'and RJ' corresponding to the jth digit of said set; a decoding circuitcoupled to said register for continuously producing an analoguereference signal corresponding to a digital number in said register; acomparator circuit coupled to said decoding circuit and responsive tosaid reference signal and to the analogue input signal for producing asignal Co having l and 0 representing levels respectively indicating thepositive and negative sense of the difference between said referencesignal and the analogue input signal; a control circuit coupled to saidregister and said comparator circuit and being responsive to saidilip-iiop signals and to signals C0 for setting said tiip-ops, one at atime in descending order of place, to stable states representing thedigital equivalent of the analogue input signal, said control circuitincluding rst means for initially setting said liip-rlops tol-representing states, second means for sequentially setting saidflip-flops to O-representing stable states, and third means operable inresponse to the l-representing level of signal C0 for resetting saidflip-flops to O-representing states after said Hip-flops are set tol-representing states, respectively.

9. An electronic converter for forming a different set of N digitaloutput signals corresponding to each of a plurality of analogue inputsignals, one digital signal of each output set being formed at a time indescending order of place, said converter comprising: a registerincluding N flip-deps and producing N signals corresponding to saiddigital signals, respectively; decoding means coupled to said registerfor continuously producing a reference signal having a levelcorresponding to the setting of said register; comparator circuit meanscoupled to said decoding means and responsive to said reference signaland to an applied analogue signal for producing comparator signals Coand when said reference signal is greater and less than the appliedanalogue signal, respectively; circuit means for electrically applyingthe analogue input signals to said comparator means, one analogue signalbeing applied during the of digital signals;

References Cited in the le of this patent UNITED STATES PATENTS2,521,733 Lesti Sept. l2, 1950 2,537,427 Seid Jan. 9, 1951 2,539,623Heising Ian. 30, 1951 2,568,724 Earp Sept. 25, 1951 2,616,965 HoeppnerNov. 4, 1952

